1. Field of the Invention
The present invention relates to a data receiver and controller for a double data rate (DDR) memory, and more particularly, to a data receiver and controller applicable to every generation of DDR memories.
2. Description of the Prior Art
In normal memories, read and write operations take place only on the rising or falling edge of a clock signal, but data in double data rate (DDR) memories are read and written both on rising edges and falling edges of the clock signal. Accordingly, DDR memories can provide doubled data throughput compared to the single data rate memories. So far there are four generations of DDR memories available in the market, including DDR1, DDR2, DDR3 and DDR4. According to the specifications of the DDR memories, different generations of DDR memories have different operating voltages, such that different signal swings possess in the data interface of different generations of DDR memories. For example, the signal level “High” in DDR1 equals 2.5V, in DDR2 equals 1.8V, in DDR3 equals 1.5V, and in DDR4 equals 1.2V.
Since the signal swings are different in different generations of DDR memories, different types or structures of data receivers have been developed. However, in the conventional data receiver, a higher power supply voltage (e.g., the I/O voltage) is applied in the input stage circuit, in order to receive the data signal from the DDR memory, where the signal swing of the DDR memory should be within the domain of the I/O voltage. The data signal is then transmitted to the core voltage domain, where two power supplies (the I/O voltage and the core voltage) are necessary in the data receiver, and the usage of I/O voltage requires more power. Further, the conventional data receivers are adaptive to at most one or two of the DDR generations since the signal swings of different DDR generations are different. Thus, there is a need to provide a novel data receiver which is adaptive to every generation of DDR memories and also has the benefits of less power consumption.